Data storage is one of the key elements in information technology. The ever increasing demand for more storage capacity in an ever shrinking form factor as well as the pressure to decrease the price per storage unit have been a major driving force for substantial world-wide research and development activities related to data storage devices such as magnetic hard drives, optical devices and silicon-based semiconductor memory chips. However, increasing the storage density is becoming increasingly difficult because conventional technologies appear to be approaching fundamental limits.
There is a need for solutions which permit still higher density data storage. Techniques using nanometer-sharp tips for imaging and investigating the structure of materials down to the nanometer scale, such as the atomic force and the scanning tunneling microscope, are suitable for the development of ultrahigh-density storage devices. Probe-based storage technologies can be regarded as natural candidates for extending the physical limits that are being approached by conventional storage technologies.
A solution to achieve high data rates of probe-based storage devices is to employ MEMS (Micro-Electro-Mechanical System) based arrays of cantilevers operating in parallel, with each cantilever comprising a tip for performing write/read/erase operations on an individual storage field. In order to obtain a high storage density, small and sharp tips are needed.
As described in prior art, crystalline silicon may be used for forming such tips. In US 2007/0041238 a process is described for the formation of silicon tips, the process comprising forming a hardmask layer over a silicon substrate, defining a pattern within the hardmask layer, wherein the pattern defines the tip area, isotropically etching the silicon to form a nascent tip structure surrounded by a shallow cavity, and growing a thermal oxide consuming additional silicon. In a subsequent step, the thermal oxide is etched, thereby causing the hardmask positioned over the tip structure to fall off and leaving a silicon tip. Additional thermal oxidation and oxide etching steps can be applied in order to adjust the height of the silicon tips and/or the radius of the curvature of the silicon tip.
When processing such tips on top of already formed circuitry, the maximum temperature allowed is limited, e.g. for CMOS circuitry limited to 450° C. Thermal oxidation of silicon is usually performed at a temperature between 800 and 1200° C., hence it is a disadvantage of the method described that it cannot be used for the formation of tips on top of already processed electrical circuitry, e.g. CMOS circuitry.
There is a need for a simple and reproducible process for forming small and sharp tips, e.g. on a cantilever, wherein the process temperature does not exceed 450° C.